Description
VHDL hardware designs can be simulated with the LLVM backend.
This is hardware description language tooling. It is useful for FPGA, ASIC, and digital logic workflows before synthesis or hardware testing.
FICHA · AUR
ghdl-llvm-git
VHDL simulator - LLVM back-end
- vhdl-simulator
- CLI
- DEVELOPER-TOOL
- ELECTRONICS
- Launchable
- Runs in terminal
official+codex · reviewed · May 31, 2026 description in
en How to run
ghdl
Commands: ghdl
Permissions
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