Description
VHDL designs can be synthesized through a Yosys plugin based on GHDL.
This is hardware synthesis tooling. It is useful in FPGA and digital design flows, but generated netlists should be verified before hardware use.
FICHA · AUR
ghdl-yosys-plugin-git
VHDL synthesis (based on ghdl and yosys)
- vhdl-synthesis-plugin
- PLUGIN
- DEVELOPER-TOOL
- ELECTRONICS
- Dependency only
official+codex · reviewed · May 31, 2026 description in
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