FICHA · AUR

qtrvsim-git

RISC-V CPU simulator for education purposes

  • riscv simulator
  • GUI
  • Launchable
official+codex · reviewed · Jun 4, 2026 description in en

Description

Current qtrvsim development builds support RISC-V education and CPU-behavior experiments. Install it when recent upstream simulator changes are needed for teaching or coursework. Simulated output should be checked against course expectations or hardware references.

How to run

qtrvsim

Commands: qtrvsim

Permissions

Permissions not analysed for this source yet.