Description
Translates synthesizable VHDL into Verilog 2001 for hardware design migration and tool compatibility. HDL developers run it from the terminal; generated Verilog should be reviewed and simulated before synthesis.
FICHA · AUR
Translate synthesizable VHDL into Verilog 2001
en Translates synthesizable VHDL into Verilog 2001 for hardware design migration and tool compatibility. HDL developers run it from the terminal; generated Verilog should be reviewed and simulated before synthesis.
vhd2vl
Commands: vhd2vl
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